The Second Edition of

IEEE Semicon Conclave 2026

Theme: Chips for Viksit Bharat

๐Ÿ“… June 5, 2026 ๐Ÿ“ Intel Bangalore
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200+
Expected Attendees
10+
Industry Speakers
1
Technical Track
1
Day of Innovation

India's Premier Semiconductor Forum

The IEEE Bangalore Semicon Conclave 2026, now in its second edition, builds on the strong foundation laid by its inaugural theme, โ€œBeyond Moore with Chiplets: Co-Optimization for Next-Gen Semiconductors.โ€

As a flagship annual event, the conclave brings together industry leaders, academic researchers, startup innovators, and policymakers to accelerate Indiaโ€™s semiconductor journey.

Centered around the theme Chips for Viksit Bharat, this yearโ€™s edition expands the conversation from next-generation architectures to nation-scale impact, spotlighting Indiaโ€™s transformative ambitions in semiconductor manufacturing, AI-driven chip design, and resilient global supply chains. It explores how India can evolve from a technology participant to a strategic leader in the global semiconductor ecosystem.

The conclave uniquely blends global technology perspectives with India-centric execution insights, creating a platform where deep-tech innovation meets policy direction, and ideas translate into scalable action and meaningful collaborations.

Semicon Conclave Logo

What We're Discussing

01

Semiconductor Manufacturing in India

Fab infrastructure, OSAT development, government policy, and the roadmap to domestic production.

02

AI Integration

How generative AI and machine learning are transforming processor architecture.

03

Advanced Nodes

2nm and beyond, chiplet architectures, and advanced heterogeneous integration.

04

Supply-Chain

Strategies for memory technology, and India's role in global supply chains.

05

Automotive Silicon

India-designed chips for automotive and ADAS applications โ€” opportunities for Indian fabless.

06

Startup & Ecosystem Growth

Scaling Indian fabless companies, EDA tools, IP ecosystem, and fostering a deep talent pipeline.

Who Should Attend?

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Semiconductor Professionals

Engineers and architects working in chip design and process technology.

๐Ÿ”ฌ

Researchers & Academicians

Faculty and researchers advancing the frontiers of semiconductor science.

๐ŸŽ“

Students & Enthusiasts

Graduate students seeking exposure to industry trends and mentorship.

๐Ÿ’ผ

Industry Leaders

Decision-makers shaping semiconductor strategy and investment in India.

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Startup Founders

Fabless startups, EDA companies, and IP providers connecting with the ecosystem.

Featured Speakers

Surya Prekke

Surya Prekke

Vice President-Engineering, Intel Corporation

Balajee Sowrirajan

Balajee Sowrirajan

Vice President, Intel Corporation

Paul Ilanghovan T

Paul Ilanghovan T

Head of Operations, Kaynes Semicon Pvt. Ltd.

Venkata Vanukuru

Venkata Vanukuru

VP of Analog IP & RF, Bharat Semi

Arun Chandrasekhar

Arun Chandrasekhar

Senior Principal Engineer, Intel

Digbijoy Neelim Nath

Digbijoy Neelim Nath

CTO & Co-founder, AGNIT Semiconductors Pvt. Ltd.

Vishal Shah

Vishal Shah

Director of Product Engineering, LTSCT

Gautam Doshi

Gautam Doshi

Chief Architect/Co-Founder at InCore Semiconductor

Rituparna Mandal

Rituparna Mandal

Past VP & Head, Synopsys India

Jayesh Gaur

Jayesh Gaur

Distinguished Engineer, IBM

Nikul Shah

Nikul Shah

Co-Founder & CEO, IndeSemiC

Preetam Tadeparthy

Preetam Tadeparthy

Co-Founder & CTO, C2i Semiconductors

Anand Mohan Pappu

Anand Mohan Pappu

Director, Auto BMS, Renesas

Conclave Agenda

08:00 AM

Registration & Networking Breakfast

09:00 AM

Opening Remarks & Welcome Note

Prasant Misra, Chair , IEEE Bangalore Section (Opening Remarks & Setting the Context);
Surya Prekke, Vice-President, Engineering, Intel (Welcome Note)
09:30 AM

KEYNOTE: Reimagining Physical Design with Agentic AI

Balajee Sowrirajan, Vice-President, Intel Corporation
10:15 AM

PLENARY-1: Indiaโ€™s OSAT Journey: Challenges, Opportunities, and the Road Ahead

Paul Ilangaon, Head of Operations, Kaynes Semicon
11:00 AM

Morning Networking Break

11:15 AM

PLENARY-2: Packaging Keeps Moore's law scaling going

Arun Chandrasekhar, Sr. Principal Engineer, Intel
12:00 PM

PANEL DISCUSSION (ISM 2.2): From Fabless to Fabricated: What Will It Take to Make Silicon in India?

Moderator: Venkata Vanukuru, VP of Analog IP & RF, Bharat Semi

Panelists:
Digbijoy Neelim Nath (CTO, AGNIT Semiconductor),
Rituparna Mandal (Past VP & Head, Synopsys India),
Vishal Shah (Director of Product Engineering, LTSCT),
Gautam Doshi (Chief Architect/Co-Founder at InCore Semiconductors)
01:00 PM

Lunch Break

02:00 PM

DEEP TECH SESSION 1: Architecture for AI & HPC Systems

Jayesh Gaur, Distinguished Engineer, IBM Distinguished Engineer
02:30 PM

DEEP TECH SESSION 2: From Silicon to Systems Integration

Nikul S., Co-Founder & CEO, IndeSemiC
03:00 PM

DEEP TECH SESSION 3: Startup Talk – Scaling Indian Fabless Companies

Preetam Tadeparthy, Co-Founder & CTO, C2i
03:30 PM

Afternoon Networking Break

03:45 PM

CLOSING PLENARY: Analog & Mixed-Signal Design: The Hidden Backbone of Smart Systems

Anand Pappu, Director, Auto BMS, Renesas
04:30 PM

Thank You Note & Feedbacks

Anindya Saha, Vice-Chair, IEEE Bangalore Section
Chengappa Munjandira, Chair-Elect, IEEE Bangalore Section

Speaker confirmed TBD

Committee Members

Prasant Misra

Prasant Misra

Anindya Saha

Anindya Saha

Chengappa Munjandira

Chengappa Munjandira

Dileep Paruchuri

Dileep Paruchuri

Jayesh Tanwani

Jayesh Tanwani

Parvathi Rachakonda

Parvathi Rachakonda

Sarfraz Hussain

Sarfraz Hussain

Sajal Mittal

Sajal Mittal

Vishal Rathod

Vishal Rathod

Kavitha Nagarajan

Kavitha Nagarajan

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Location

๐Ÿ“

Intel ECO3 Building

Bellandur, Bengaluru

Intel India Technology Pvt Ltd

RMZ Ecospace Business Park, Outer Ring Road
Bellandur, Bengaluru, Karnataka 560103
(First left once you enter RMZ Ecospace Campus)

Google Coordinates: https://share.google/UpJt7TJRzA4ECLw1x

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